MC68HC908GT16_07 Datasheet, PDF (209/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

16.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 16-1.
Table 16-1. SPI Interrupts
Flag
SPTE — Transmitter empty
SPRF — Receiver full
OVRF — Overflow
MODF — Mode fault
Request
SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1)
SPI receiver CPU interrupt request (SPRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
Interrupts
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables SPRF to generate receiver CPU interrupt requests,
regardless of the state of SPE. See Figure 16-12.
SPTE SPTIE _SPE
SPRIE SPRF
SPI TRANSMITTER
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 16-12. SPI Interrupt Request Generation
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error
CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
The following sources in the SPI status and control register can generate CPU interrupt requests:
• SPI receiver full bit (SPRF) — SPRF becomes set every time a byte transfers from the shift register
to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF
generates an SPI receiver/error CPU interrupt request.
• SPI transmitter empty (SPTE) — SPTE becomes set every time a byte transfers from the transmit
data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE
generates an SPTE CPU interrupt request.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
209