MC68HC908GT16_07 Datasheet, PDF (87/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
CMON
IREF
ECLK
R
D
DFFRS
CK Q
S
CK Q
1/4
R
R
D
DFFRR
CK Q
R
EOFF
EGGS
ESTBCLK
ECGEN
NAME
NAME
CONFIG2 REGISTER BIT
NAME
REGISTER BIT
TOP LEVEL SIGNAL
NAME
MODULE SIGNAL
Figure 7-7. External Clock Activity Detector
7.3.5 Clock Selection Circuit
The clock selection circuit, shown in Figure 7-8, contains two clock switches which generate the oscillator
output clock (CGMXCLK) and the timebase clock (TBMCLK) from either the internal clock (ICLK) or the
external clock (ECLK). The COP clock (COPCLK) is identical to TBMCLK. The clock selection circuit also
contains a divide-by-two circuit which creates the clock generator output clock (CGMOUT), which
generates the bus clocks.
CS
ICLK
ECLK
IOFF
EOFF
RESET
V_SS
ECGON
SELECT
OUTPUT
ICLK
ECLK _{SYNCHRONIZING}
DIV2
IOFF
CLOCK
EOFF
SWITCHER
FORCE_I
FORCE_E
SELECT
OUTPUT
ICLK
ECLK
IOFF
EOFF
SYNCHRONIZING
CLOCK
SWITCHER
FORCE_I
FORCE_E
CGMXCLK
CGMOUT
TBMCLK
COPCLK
NAME
CONFIG2 REGISTER BIT
NAME
REGISTER BIT
NAME
TOP LEVEL SIGNAL
NAME
MODULE SIGNAL
Figure 7-8. Clock Selection Circuit Block Diagram
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
87