MC68HC908GT16_07 Datasheet, PDF (85/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

CMON
FICGS
IBASE
ICGEN
EXTXTALEN
EXTSLOW
CMON
FICGS
IBASE
ICGEN
ICLK
ACTIVITY
DETECTOR
EREF
IOFF
ICGS
IBASE
ICGON
EREF
EXTXTALEN
EXTSLOW
ECGS
REFERENCE
GENERATOR
ECLK
ECGEN
ESTBCLK
IREF
Functional Description
IOFF
ICGS
ECGEN
ECLK
ESTBCLK
IREF
ECGEN
ECLK
ECLK
ACTIVITY
DETECTOR
ECGS
CMON
EOFF
ECGS
EOFF
NAME
CONFIG2 REGISTER BIT
NAME
REGISTER BIT
NAME
TOP LEVEL SIGNAL
NAME
Figure 7-5. Clock Monitor Block Diagram
MODULE SIGNAL
To conserve size, the long divider (divide by 4096) is also used as an external crystal stabilization divider.
The divider is reset when the external clock generator is turned off or in stop mode (ECGEN is clear).
When the external clock generator is first turned on, the external clock generator stable bit (ECGS) will
be clear. This condition automatically selects ECLK as the input to the long divider. The external
stabilization clock (ESTBCLK) will be ECLK divided by 16 when EXTXTALEN is low or 4096 when
EXTXTALEN is high. This timeout allows the crystal to stabilize. The falling edge of ESTBCLK is used to
set ECGS, which will set after a full 16 or 4096 cycles. When ECGS is set, the divider returns to its normal
function. ESTBCLK may be generated by either IBASE or ECLK, but any clocking will only reinforce the
set condition. If ECGS is cleared because the clock monitor determined that ECLK was inactive, the
divider will revert to a stabilization divider. Since this will change the EREF and IREF divide ratios, it is
important to turn the clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
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