MC68HC908GT16_07 Datasheet, PDF (63/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

COP Control Register
5.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
5.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 4 Configuration Register (CONFIG).
5.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See
Chapter 4 Configuration Register (CONFIG).
5.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
Read:
5
4
3
2
Low byte of reset vector
1
Bit 0
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 5-2. COP Control Register (COPCTL)
5.5 Interrupts
The COP does not generate central processor unit (CPU) interrupt requests.
5.6 Monitor Mode
When monitor mode is entered with V_TST on the IRQ pin, the COP is disabled as long as V_TST remains
on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V_TST on the IRQ pin, the COP is automatically disabled until a POR occurs.
5.7 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby
modes.
5.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear
the COP counter in a CPU interrupt routine.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
63