MC68HC908GT16_07 Datasheet, PDF (95/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

CONFIG2 Options
7.5.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG2 register determines the
behavior of the ICG in stop mode. If OSCENINSTOP is low, the ICG is disabled in stop and, upon
execution of the STOP instruction, all ICG activity will cease and the output clocks (CGMXCLK,
CGMOUT, COPCLK, and TBMCLK) will be held low. Power consumption will be minimal.
If OSCENINSTOP is high, the ICG is enabled in stop and activity will continue. This is useful if the
timebase module (TBM) is required to bring the MCU out of stop mode. ICG interrupts will not bring the
MCU out of stop mode in this case.
During stop mode, if OSCENINSTOP is low, several functions in the ICG are affected. The stable bits
(ECGS and ICGS) are cleared, which will enable the external clock stabilization divider upon recovery.
The clock monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE)
and clock monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are
unaffected.
7.6 CONFIG2 Options
Four CONFIG2 register options affect the functionality of the ICG. These options are:
1. EXTCLKEN, external clock enable
2. EXTXTALEN, external crystal enable
3. EXTSLOW, slow external clock
4. OSCENINSTOP, oscillator enable in stop
All CONFIG2 options will have a default setting. Refer to Chapter 4 Configuration Register (CONFIG) on
how the CONFIG2 register is used.
7.6.1 External Clock Enable (EXTCLKEN)
External clock enable (EXTCLKEN), when set, enables the ECGON bit to be set. ECGON turns on the
external clock input path through the PTE4/OSC1 pin. When EXTCLKEN is clear, ECGON cannot be set
and PTE4/OSC1 will always perform the PTE4 function.
The default state for this option is clear.
7.6.2 External Crystal Enable (EXTXTALEN)
External crystal enable (EXTXTALEN), when set, will enable an amplifier to drive the PTE3/OSC2 pin
from the PTE4/OSC1 pin. The amplifier will drive only if the external clock enable (EXTCLKEN) bit and
the ECGON bit are also set. If EXTCLKEN or ECGON are clear, PTE3/OSC2 will perform the PTE3
function. When EXTXTALEN is clear, PTE3/OSC2 will always perform the PTE3 function.
EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the valid
range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock monitor
will expect an external clock source in the valid range for externally generated clocks when using the clock
monitor (60 Hz to 32 MHz).
EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for a
4096 cycle timeout to allow the proper stabilization time for a crystal. When EXTXTALEN is clear, the
stabilization divider is configured to 16 cycles since an external clock source does not need a startup time.
The default state for this option is clear.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
95