MC68HC908GT16_07 Datasheet, PDF (135/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

12.6.1 Port E Data Register
The port E data register contains a data latch for each of the five port E pins.
Port E
Address: $0008
Bit 7
6
Read: 0
0
Write:
Reset:
Alternative Function:
5
4
3
2
1
Bit 0
0
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by reset
OSC1 OSC2
RxD
TxD
= Unimplemented
Figure 12-17. Port E Data Register (PTE)
PTE4-PTE0 — Port E Data Bits
These read/write bits are software-programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port Edata.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 12-6.
OSC2 and OSC1 — OSC2 and OSC1 Bits
Under software control, PTE4 and PTE3 can be configured as external clock inputs and outputs. PTE3
will become an output clock, OSC2, if selected in the configuration registers and enabled in the ICG
registers. PTE4 will become an external input clock source, OSC1, if selected in the configuration
registers and enabled in the ICG registers. See Chapter 7 Internal Clock Generator (ICG) Module) and
Chapter 5 Computer Operating Properly (COP) Module. While configured as oscillator pins, writes
have no effect and reads return undefined values.
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module.
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1
to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
135