MC68HC908GT16_07 Datasheet, PDF (51/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

INTERNAL DATA BUS
READ DDRBx
WRITE DDRBx
RESET
WRITE PTBx
READ PTBx
DDRBx
PTBx
Functional Description
DISABLE
PTBx
ADC CHANNEL x
INTERRUPT
LOGIC
CONVERSION
COMPLETE
AIEN COCO
CGMXCLK
BUS CLOCK
DISABLE
ADC DATA REGISTER
ADC
ADC
VOLTAGE IN
(V_ADIN)
V_REFH
V_REFL
CHANNEL
SELECT
ADCH4–ADCH0
ADC CLOCK
CLOCK
GENERATOR
ADIV2–ADIV0
ADICLK
Figure 3-2. ADC Block Diagram
3.3.2 ADC Port I/O Pins
PTB7/AD7–PTB0/AD0 are general-purpose I/O pins that share with the ADC channels. The channel
select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port
I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by
the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction
register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in
use by the ADC will return a logic 0.
3.3.3 Voltage Conversion
When the input voltage to the ADC equals V_REFH, the ADC converts the signal to $FF (full scale). If the
input voltage equals V_REFL, the ADC converts it to $00. Input voltages between V_REFH and V_REFL are a
straight-line linear conversion.
NOTE
The ADC input voltage must always be greater than V_SSA and less than
V_DDA. V_REFH must always be greater than or equal to V_REFL.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
51