MC68HC908GT16_07 Datasheet, PDF (81/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

ICGEN
VOLTAGE AND
CURRENT
REFERENCES
++
+
DIGITAL
LOOP
FILTER
–
––
TRIM[7:0]
FREQUENCY
COMPARATOR
CLOCK GENERATOR
DIGITALLY
CONTROLLED
OSCILLATOR
N[6:0]
MODULO
N
DIVIDER
Functional Description
FICGS
DSTG[7:0]
DDIV[3:0]
ICLK
IBASE
NAME
NAME
CONFIG2 REGISTER BIT
TOP LEVEL SIGNAL
NAME
NAME
REGISTER BIT
MODULE SIGNAL
Figure 7-3. Internal Clock Generator Block Diagram
7.3.2.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock
(ICLK). The clock period of ICLK is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]).
Because of only a limited number of bits in DDIV and DSTG, the precision of the output (ICLK) is restricted
to a precision of approximately ±0.202 percent to ±0.368 percent when measured over several cycles (of
the desired frequency). Additionally, since the propagation delays of the devices used in the DCO ring
oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require
alternately running faster and slower than desired, making the worst case cycle-to-cycle frequency
variation ±6.45 percent to ±11.8 percent (of the desired frequency). The valid values of DDIV:DSTG range
from $000 to $9FF. For more information on the quantization error in the DCO, see 7.4.4 Quantization
Error in DCO Output.
7.3.2.2 Modulo N Divider
The modulo N divider creates the low-frequency base clock (IBASE) by dividing the internal clock (ICLK)
by the ICG multiplier factor (N), contained in the ICG multiplier register (ICGMR). When N is programmed
to a $01 or $00, the divider is disabled and ICLK is passed through to IBASE undivided. When the internal
clock generator is stable, the frequency of IBASE will be equal to the nominal frequency (f_NOM) of 307.2
kHz ± 25 percent.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
81