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MC68HC908GT16_07 Datasheet, PDF (213/292 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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16.12 I/O Registers
Three registers control and monitor SPI operation:
⢠SPI control register (SPCR)
⢠SPI status and control register (SPSCR)
⢠SPI data register (SPDR)
I/O Registers
16.12.1 SPI Control Register
The SPI control register:
⢠Enables SPI module interrupt requests
⢠Configures the SPI module as master or slave
⢠Selects serial clock polarity and phase
⢠Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
⢠Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
Read:
SPRIE
Write:
R
SPMSTR CPOL CPHA SPWOM SPE
Reset:
0
0
1
0
1
0
0
R = Reserved
Figure 16-14. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE â SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR â SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
CPOL â Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure
16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical
CPOL values. Reset clears the CPOL bit.
CPHA â Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure
16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be high between bytes. (See
Figure 16-13.) Reset sets the CPHA bit.
MC68HC908GT16 ⢠MC68HC908GT8 ⢠MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
213
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