MC68HC908GT16_07 Datasheet, PDF (58/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG)
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
Reset: 0
0
0
EXTXTALEN EXTSLOW EXTCLKEN
OSCENINSTOP R
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 4-1. Configuration Register 2 (CONFIG2)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
Write:
Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3
0
0
0
See Note
SSREC
0
STOP
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 4-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
EXTXTALEN — External Crystal Enable Bit
EXTXTALEN enables the external oscillator circuits to be configured for a crystal configuration where
the PTE4/OSC1 and PTE3/OSC2 pins are the connections for an external crystal.
Clearing the EXTXTALEN bit (default setting) allows the PTE3/OSC2 pin to function as a
general-purpose I/O pin. Refer to Table 4-1 for configuration options for the external source. See
Chapter 7 Internal Clock Generator (ICG) Module) for a more detailed description of the external clock
operation.
EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the
valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock
monitor will expect an external clock source in the valid range for externally generated clocks when
using the clock monitor (60 Hz to 32 MHz).
EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for
a 4096-cycle timeout to allow the proper stabilization time for a crystal. When EXTXTALEN is clear,
the stabilization divider is configured to 16 cycles since an external clock source does not need a
startup time.
1 = Allows PTE3/OSC2 to be an external crystal connection.
0 = PTE3/OSC2 functions as an I/O port pin (default).
EXTSLOW — Slow External Crystal Enable Bit
The EXTSLOW bit has two functions. It configures the ICG module for a fast (1 MHz to 8 MHz) or slow
(30 kHz to 100 kHz) speed crystal. The option also configures the clock monitor operation in the ICG
module to expect an external frequency higher (307.2 kHz to 32 MHz) or lower (60 Hz to 307.2 kHz)
than the base frequency of the internal oscillator. See Chapter 7 Internal Clock Generator (ICG)
Module).
1 = ICG set for slow external crystal operation
0 = ICG set for fast external crystal operation
NOTE
This bit does not function without setting the EXTCLKEN bit also.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
58
Freescale Semiconductor