MC68HC908GT16_07 Datasheet, PDF (192/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt or break interrupt interrupt
Figure 15-16. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 15-17. Wait Recovery from Internal Reset
15.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in CONFIG1. If SSREC
is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal
for applications using canned oscillators that do not require long startup times from stop mode.
NOTE
All applications should use the full stop recovery time by clearing the
SSREC bit unless OSCENINSTOP is set in CONFIG2.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 15-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
192
Freescale Semiconductor