MC68HC908GT16_07 Datasheet, PDF (52/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
NOTE
Connect the V_DDA pin to the same voltage potential as the V_DD pin, and
connect the V_SSA pin to the same voltage potential as the V_SS pin. The
V_DDA pin should be routed carefully for maximum noise immunity.
3.3.4 Conversion Time
Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take
between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC
clock frequency.
Conversion time = ^{16 to 17 ADC cycles}
ADC frequency
Number of bus cycles = conversion time × bus frequency
3.3.5 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and
will stay set until the next read of the ADC data register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs
between writes to the ADSCR.
When a conversion is in process and the ADSCR is written, the current conversion data should be
discarded to prevent an incorrect reading.
3.3.6 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
3.5 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power-consumption standby modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
52
Freescale Semiconductor