MC68HC908GT16_07 Datasheet, PDF (143/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
Interrupts
13.3.2 Sources
The sources in Table 13-1 can generate CPU interrupt requests.
13.3.2.1 Software Interrupt (SWI) Instruction
The software interrupt instruction (SWI) causes a non-maskable interrupt.
NOTE
A software interrupt pushes PC onto the stack. An SWI does not push PC
– 1, as a hardware interrupt does.
Table 13-1. Interrupt Sources
Source
Reset
SWI instruction
IRQ pin
ICG clock monitor
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receiver full
SPI overflow
SPI mode fault
SPI transmitter empty
SCI receiver overrun
SCI noise fag
SCI framing error
SCI parity error
SCI receiver full
SCI input idle
SCI transmitter empty
SCI transmission complete
Keyboard pin
ADC conversion complete
Timebase
Flag
None
None
IRQF
CMF
CH0F
CH1F
TOF
CH0F
CH1F
TOF
SPRF
OVRF
MODF
SPTE
OR
NF
FE
PE
SCRF
IDLE
SCTE
TC
KEYF
COCO
TBIF
Mask⁽¹⁾
None
None
IMASK1
CMIE
CH0IE
CH1IE
TOIE
CH0IE
CH1IE
TOIE
SPRIE
ERRIE
ERRIE
SPTIE
ORIE
NEIE
FEIE
PEIE
SCRIE
ILIE
SCTIE
TCIE
IMASKK
AIEN
TBIE
INT Register
Flag
None
None
IF1
IF2
IF3
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
IF12
IF13
IF14
IF15
IF16
Priority⁽²⁾
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vector Address
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF8–$FFF9
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
$FFEE–$FFEF
$FFEC–$FFED
$FFEA–$FFEB
$FFE8–$FFE9
$FFE6–$FFE7
$FFE4–$FFE5
$FFE2–$FFE3
$FFE0–$FFE1
$FFDE–$FFDF
$FFDC–$FFDD
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
143