MC68HC908GT16_07 Datasheet, PDF (88/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Generator (ICG) Module)
7.3.5.1 Clock Selection Switches
The first switch creates the oscillator output clock (CGMXCLK) from either the internal clock (ICLK) or the
external clock (ECLK), based on the clock select bit (CS; set selects ECLK, clear selects ICLK). When
switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock being
switched to also must be stable (ICGS or ECGS set).
The second switch creates the timebase clock (TBMCLK) and the COP clock (COPCLK) from ICLK or
ECLK based on the external clock on bit. When ECGON is set, the switch automatically selects the
external clock, regardless of the state of the ECGS bit.
7.3.5.2 Clock Switching Circuit
To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes
the clocks are completely asynchronous, so a synchronizing circuit is required to make the transition.
When the select input (the clock select bit for the oscillator output clock switch or the external clock on bit
for the timebase clock switch) is changed, the switch will continue to operate off the original clock for
between one and two cycles as the select input is transitioned through one side of the synchronizer. Next,
the output will be held low for between one and two cycles of the new clock as the select input transitions
through the other side. Then the output starts switching at the new clock’s frequency. This transition
guarantees that no glitches will be seen on the output even though the select input may change
asynchronously to the clocks. The unpredictably of the transition period is a necessary result of the
asynchronicity.
The switch automatically selects ICLK during reset. When the clock monitor is on (CMON is set) and it
determines one of the clock sources is inactive (as indicated by the IOFF or EOFF signals), the circuit is
forced to select the active clock. There are no clocks for the inactive side of the synchronizer to properly
operate, so that side is forced deselected. However, the active side will not be selected until one to two
clock cycles after the IOFF or EOFF signal transitions.
7.4 Usage Notes
The ICG has several features which can provide protection to the microcontroller if properly used. Other
features can greatly simplify usage of the ICG if certain techniques are employed. This section describes
several possible ways to use the ICG and its features. These techniques are not the only ways to use the
ICG and may not be optimum for all environments. In any case, these techniques should be used only as
a template, and the user should modify them according to the application’s requirements.
These notes include:
• Switching clock sources
• Enabling the clock monitor
• Using clock monitor interrupts
• Quantization error in digitally controlled oscillator (DCO) output
• Switching internal clock frequencies
• Nominal frequency settling time
• Improving frequency settling time
• Trimming frequency
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
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Freescale Semiconductor