MC68HC908GT16_07 Datasheet, PDF (180/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO ICG)
CGMXCLK (FROM ICG)
CGMOUT (FROM ICG)
÷2
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
FORCED MONITOR MODE ENTRY
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 15-1. SIM Block Diagram
Addr. Register Name
Bit 7
6
SIM Break Status Register ^Read:
R
R
$FE00
(SBSR) Write:
See page 193. _Reset:
0
0
Note: Writing a 0 clears SBSW.
SIM Reset Status Register ^{Read: POR}
PIN
$FE01
(SRSR) Write:
See page 194. _POR:
1
0
Read:
$FE02
SIM Upper Byte Address
Register (SUBAR)
Write:
R
R
Reset:
5
4
3
R
R
R
0
0
0
COP
ILOP
ILAD
0
0
0
R
R
R
Figure 15-2. SIM I/O Register Summary
2
1
SBSW
R
NOTE
0
0
MODRST LVI
0
0
R
R
Bit 0
R
0
0
0
R
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
180
Freescale Semiconductor