MC68HC908GT16_07 Datasheet, PDF (100/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Generator (ICG) Module)
7.7.3 ICG Trim Register
Address: $0038
Bit 7
Read:
TRIM7
Write:
Reset:
1
6
5
4
3
2
TRIM6 TRIM5 TRIM4 TRIM3 TRIM2
0
0
0
0
0
Figure 7-14. ICG Trim Register (ICGTR)
1
TRIM1
0
Bit 0
TRIM0
0
TRIM7:TRIM0 — ICG Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved to ± 2 percent. Incrementing this register by one
decreases the frequency by 0.195 percent of the unadjusted value. Decrementing this register by one
increases the frequency by 0.195 percent. This register cannot be written when the CMON bit is set.
Reset sets these bits to $80, centering the range of possible adjustment.
7.7.4 ICG DCO Divider Register
Address: $0039
Bit 7
Read:
Write:
Reset:
0
6
5
0
0
= Unimplemented
4
3
2
1
Bit 0
DDIV3 DDIV2 DDIV1 DDIV0
0
U
U
U
U
U = Unaffected
Figure 7-15. ICG DCO Divider Control Register (ICGDVR)
DDIV3:DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A through $F are interpreted the same as $9. Since the DCO is active during
reset, reset has no effect on DSTG and the value may vary.
7.7.5 ICG DCO Stage Register
Address: $003A
Bit 7
Read: DSTG7
Write: R
Reset:
R
6
DSTG6
R
5
DSTG5
R
= Reserved
4
3
DSTG4 DSTG3
R
R
Unaffected by reset
2
DSTG2
R
1
DSTG1
R
Figure 7-16. ICG DCO Stage Control Register (ICGDSR)
Bit 0
DSTG0
R
DSTG7:DSTG0 — ICG DCO Stage Control Bits
These bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. The
total number of stages is approximately equal to $1FF, so changing DSTG from $00 to $FF will
approximately double the period. Incrementing DSTG will increase the period (decrease the
frequency) by 0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG cannot
be written when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is
controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG
and the value may vary.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
100
Freescale Semiconductor