MC68HC908GT16_07 Datasheet, PDF (93/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Usage Notes
Settling time depends primarily on how many corrections it takes to change the clock period and the
period of each correction. Since the corrections require four periods of the low-frequency base clock
(4*τ_IBASE), and since ICLK is N (the ICG multiply factor for the desired frequency) times faster than
IBASE, each correction takes 4*N*τ_ICLK. The period of ICLK, however, will vary as the corrections occur.
7.4.6.1 Settling to Within 15 Percent
When the error is greater than 15 percent, the filter takes eight corrections to double or halve the clock
period. Due to how the DCO increases or decreases the clock period, the total period of these eight
corrections is approximately 11 times the period of the fastest correction. (If the corrections were perfectly
linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly
nonlinear.) Therefore, the total time it takes to double or halve the clock period is 44*N*τ_ICLKFAST.
If the clock period needs more than doubled or halved, the same relationship applies, only for each time
the clock period needs doubled, the total number of cycles doubles. That is, when transitioning from fast
to slow, going from the initial speed to half speed takes 44*N*τ_ICLKFAST; from half speed to quarter speed
takes 88*N*τ_ICLKFAST; going from quarter speed to eighth speed takes 176*N*τ_ICLKFAST; and so on. This
series can
doubled or
be expressed
halved. Since
as
2^x
(2^x–1)*44*N*τ_ICLKFAST,
happens to be equal to
where x is the number of
τ_ICLKSLOW/τ_ICLKFAST, the
times the
equation
speed needs
reduces to
44*N*(τ_ICLKSLOW–τ_ICLKFAST).
Note that increasing speed takes much longer than decreasing speed since N is higher. This can be
expressed in terms of the initial clock period (τ₁) minus the final clock period (τ₂) as such:
τ₁₅ = abs[44N(τ₁ – τ₂)]
7.4.6.2 Settling to Within 5 Percent
Once the clock period is within 15 percent of the desired clock period, the filter starts making smaller
adjustments. When between 15 percent and 5 percent error, each correction will adjust the clock period
between 1.61 percent and 2.94 percent. In this mode, a maximum of eight corrections will be required to
get to less than 5 percent error. Since the clock period is relatively close to desired, each correction takes
approximately the same period of time, or 4*τ_IBASE. At this point, the internal clock stable bit (ICGS) will
be set and the clock frequency is usable, although the error will be as high as 5 percent. The total time to
this point is:
τ₅ = abs[44N(τ₁ – τ₂)] + 32τ_IBASE
7.4.6.3 Total Settling Time
Once the clock period is within 5 percent of the desired clock period, the filter starts making minimum
adjustments. In this mode, each correction will adjust the frequency between 0.202 percent and 0.368
percent. A maximum of 24 corrections will be required to get to the minimum error. Each correction takes
approximately the same period of time, or 4*τ_IBASE. Added to the corrections for 15 percent to 5 percent,
this makes 32 corrections (128*τ_IBASE) to get from 15 percent to the minimum error. The total time to the
minimum error is:
τ_tot = abs[44N(τ₁ – τ₂)] + 128τ_IBASE
The equations for τ₁₅, τ₅, and τ_tot are dependent on the actual initial and final clock periods τ₁ and τ₂, not
the nominal. This means the variability in the ICLK frequency due to process, temperature, and voltage
must be considered. Additionally, other process factors and noise can affect the actual tolerances of the
points at which the filter changes modes. This means a worst case adjustment of up to 35 percent (ICLK
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
93