MC68HC908GT16_07 Datasheet, PDF (232/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table
18-1 shows. Reset clears the PS[2:0] bits.
Table 18-1. Prescaler Selection
PS2
PS1
PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
18.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-6. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-7. TIM Counter Registers Low (TCNTL)
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
232
Freescale Semiconductor