MC68HC908GT16_07 Datasheet, PDF (59/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
EXTCLKEN — External Clock Enable Bit
EXTCLKEN enables an external clock source or crystal/ceramic resonator to be used as a clock input.
Setting this bit enables PTE4/OSC1 pin to be a clock input pin. Clearing this bit (default setting) allows
the PTE4/OSC1 and PTE3/OSC2 pins to function as a general-purpose input/output (I/O) pin. Refer
to Table 4-1 for configuration options for the external source. See Chapter 7 Internal Clock Generator
(ICG) Module) for a more detailed description of the external clock operation.
1 = Allows PTE4/OSC1 to be an external clock connection
0 = PTE4/OSC1 and PTE3/OSC2 function as I/O port pins (default).
Table 4-1. External Clock Option Settings
External Clock
Configuration Bits
EXTCLKEN EXTXTALEN
0
0
0
1
1
0
1
1
Pin
Function
PTE4/OSC1 PTE3/OSC2
PTE4
PTE3
PTE4
PTE3
OSC1
PTE3
OSC1
OSC2
Description
Default setting — external oscillator disabled
External oscillator disabled since EXTCLKEN not set
External oscillator configured for an external clock source
input (square wave) on OSC1
External oscillator configured for an external crystal
configuration on OSC1 and OSC2. System will also
operate with square-wave clock source in OSC1.
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable the internal clock generator module to continue to generate
clocks (either internal, ICLK, or external, ECLK) in stop mode. See Chapter 7 Internal Clock Generator
(ICG) Module). This function is used to keep the timebase running while the rest of the microcontroller
stops. See Chapter 17 Timebase Module (TBM). When clear, all clock generation will cease and both
ICLK and ECLK will be forced low during stop mode. The default state for this option is clear, disabling
the ICG in stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
NOTE
This bit has the same functionality as the OSCSTOPENB CONFIG bit in
MC68HC908GP32 and MC68HC908GR8 parts.
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. See Chapter 5 Computer Operating
Properly (COP) Module
1 = COP timeout period = 8176 COPCLK cycles
0 = COP timeout period = 262,128 COPCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
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