MC68HC05JJ6 Datasheet, PDF (87/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Parallel Input/Output
7.4.5 PB0, PBI, PB2, and PB3 Logic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and
PB3 pins of port B. When these port B pins are programmed as an
output, reading the port bit actually reads the value of the data latch and
not the voltage on the pin itself. When these port B pins are programmed
as an input, reading the port bit reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its DDRB bit.
The operations of the PB0:PB3 pins are summarized in Table 7-2.
READ $0005
WRITE $0005
WRITE $0001
READ $0001
WRITE $0011
RESET
DATA DIRECTION
REGISTER B
R
BIT DDRBx
PORT BDATA
REGISTER
BIT PBx
PULLDOWN
REGISTER B
R
BIT PDIBx
PULLDOWN INHIBIT
MASK OPTION
(ENABLE = 0)
Figure 7-8. PB0:PB3 Pin I/O Circuit
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
(PINS PB0, PB1, PB2, PB3)
PBx
100 µA
PULLDOWN
DEVICE
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Parallel Input/Output
General Release Specification
87