MC68HC05JJ6 Datasheet, PDF (64/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Resets
5.5.4 Illegal Address Reset
An opcode fetch (execution of an instruction) at an address that is not in
the ROM (locations $0700–$1FFF) or the RAM (locations
$0020–$00FF) generates an illegal address reset. The illegal address
reset will assert the pulldown device to pull the RESET pin low for three
to four cycles of the internal bus.
5.6 Reset States
The following paragraphs describe how the various resets initialize the
MCU.
5.6.1 CPU
A reset has these effects on the CPU:
• Loads the stack pointer with $FF
• Sets the I bit in the condition code register, inhibiting interrupts
• Loads the program counter with the user-defined reset vector from
locations $1FFE and $1FFF
• Clears the stop latch, enabling the CPU clock
• Clears the wait latch, bringing the CPU out of the wait mode
General Release Specification
64
Resets
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor