MC68HC05JJ6 Datasheet, PDF (53/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
NOTE:
If the port A pins are enabled by mask option as external interrupts, then
a high level on any PA0:PA3 pin will drive the state of the IRQ function
such that the IRQ pin and other PA0:PA3 pins will be ignored until ALL
of the PA0:PA3 pins have returned to a low level. Similarly, if the IRQ pin
is at a low level, the PA0:PA3 pins will be ignored until the IRQ pin
returns to a high state.
4.6.3 IRQ Status and Control Register
The IRQ status and control register (ISCR), shown in Figure 4-4,
contains an external interrupt mask (IRQE), an external interrupt flag
(IRQF), and a flag reset bit (IRQR). Unused bits will read as logic zeros.
The ISCR also contains two control bits for the oscillators, external pin
oscillator, and internal low-power oscillator. Reset sets the IRQE and
OM2 bits; and clears all the other bits.
$000D Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
IRQF
0
0
0
IRQE OM2 OM1
Write:
R
IRQR
Reset: 1
1
0
0
0
0
U
0
= Unimplemented
R
= Reserved
Figure 4-4. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
OM1 and OM2 — Oscillator Selects
These bits control the selection and enabling of the oscillator source
for the MCU. One choice is the internal low-power oscillator (LPO).
The other choice is the external pin oscillator (EPO) which is common
to most MC68HC05 MCU devices. The EPO uses external
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Interrupts
General Release Specification
53