MC68HC05JJ6 Datasheet, PDF (54/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
components like filter capacitors and a crystal or ceramic resonator
and consumes more power. The selection and enable conditions for
these two oscillators are shown in Table 4-2.
OM2 OM1
0
0
0
1
1
0
1
1
Table 4-2. Oscillator Selection
Oscillator
Selected
by CPU
Internal
External
Internal
Internal
Internal
Low-Power
Oscillator
(LPO)
Enabled
Disabled
Enabled
Enabled
External
Pin
Oscillator
(EPO)
Disabled
Enabled
Disabled
Enabled
Power
Consumption
Lowest
Normal
Lowest
Normal
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started and allowed to stabilize while the LPO still clocks the MCU. The
reset state is for OM1 to be cleared and OM2 to be set, which selects the
LPO and disables the EPO.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Writing to the IRQF bit has no effect.
Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQ flag:
• An external interrupt signal on the IRQ pin
• An external interrupt signal on pins PA0, PA1, PA2, or PA3
when the PA0 through PA3 pins are enabled by a mask option
to serve as external interrupt sources
These conditions clear the IRQ flag:
• When the CPU fetches the interrupt vector
• When a logic one is written to the IRQR bit
General Release Specification
54
Interrupts
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor