MC68HC05JJ6 Datasheet, PDF (81/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Parallel Input/Output
7.3.3 Pulldown Register A
All port A pins can have software programmable pulldown devices
enabled or disabled by a mask option. When enabled these pulldowns
can sink approximately 100 µA. These pulldown devices are controlled
by the write-only pulldown register A (PDRA) shown in Figure 7-3.
Clearing the PDIA5–PDIA0 bits in the PDRA turns on the pulldown
devices if the port A pin is an input. Reading the PDRA returns undefined
results since it is a write-only register. On the MC68HC05JJ6, the PDRA
contains two pulldown control bits (PDICH and PDICL) for port C. Reset
clears the PDIA5–PDIA0, PDICH and PDICL bits, which turns on all the
port A and port C pulldown devices.
$0010
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
PDICH PDICL PDIA5 PDIA4 PDIA3 PDIA2 PDIA1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
Bit 0
PDIA0
0
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC05JP6)
Writing to this write-only bit controls the port C pulldown devices on
the upper four bits (PC4:PC7). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICH.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC05JP6)
Writing to this write-only bit controls the port C pulldown devices on
the lower four bits (PC0:PC3). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICL.
1 = Lower four port C pins pulldown devices turned off
0 = Lower four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Parallel Input/Output
General Release Specification
81