MC68HC05JJ6 Datasheet, PDF (51/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
With the edge- and level-sensitive trigger option, a falling edge or a low
level on the IRQ pin latches an external interrupt request. The edge- and
level-sensitive trigger mask option allows connection to the IRQ pin of
multiple wired-OR interrupt sources. As long as any source is holding the
IRQ low, an external interrupt request is present, and the CPU continues
to execute the interrupt service routine.
With the edge-sensitive-only trigger mask option, a falling edge on the
IRQ pin latches an external interrupt request. A subsequent interrupt
request can be latched only after the voltage level on the IRQ pin returns
to a logic one and then falls again to logic zero.
IRQ
PA3
PA2
PA1
PA0
KEYBOARD
INTERRUPT
MASK OPTION
(ENABLE = 1)
EDGE- OR
EDGE- AND LEVEL
MASK OPTION
(ENABLE=1)
V_DD
IRQ
LATCH
R
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
RST
IRQ VECTOR FETCH
INTERNAL DATA BUS
IRQ STATUS/CONTROL REGISTER ($000D)
Figure 4-3. External Interrupt Logic
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Interrupts
General Release Specification
51