MC68HC05JJ6 Datasheet, PDF (52/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
NOTE:
The response of the IRQ pin can be affected if the external interrupt
capability of the PA0 through PA3 pins is enabled by mask option. If the
port A pins are enabled as external interrupts, then any high level on a
PA0 through PA3 pin will cause the IRQ changes and state to be ignored
until all of the PA0 through PA3 pins have returned to a low level.
4.6.2 PA0–PA3 Pins
The port A interrupt mask option that enables the PA0 through PA3 pins
(PA0:PA3) to serve as additional external interrupt sources is available.
When this mask option is enabled, a rising edge on a PA0:PA3 pin
latches an external interrupt request. After completing the current
instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
ISCR. If the I bit is clear and the IRQE bit is set, the CPU then begins the
interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched
during the interrupt service routine. As soon as the I bit is cleared during
the return from interrupt, the CPU can recognize the new interrupt
request.
The PA0:PA3 pins can be edge-triggered or edge- and level-triggered
depending upon the mask option selection for the IRQ pin.
With the edge- and level-sensitive trigger mask option, a rising edge or
a high level on a PA0:PA3 pin latches an external interrupt request. The
edge- and level-sensitive trigger mask option allows connection to a
PA0:PA3 pin of multiple wired-OR interrupt sources. As long as any
source is holding the pin high, an external interrupt request is present,
and the CPU continues to execute the interrupt service routine.
With the edge-sensitive only trigger mask option, a rising edge on a
PA0:PA3 pin latches an external interrupt request. A subsequent
external interrupt request can be latched only after the voltage level of
the previous interrupt signal returns to a logic zero and then rises again
to a logic one.
General Release Specification
52
Interrupts
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor