MC68HC05JJ6 Datasheet, PDF (142/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Simple Serial Interface
SPE — Serial Peripheral Enable
The SPE bit switches the port B interface such that SDO/PB5 is the
serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a
serial clock input in the slave mode or a serial clock output in the
master mode. The port B DDR and data registers can be manipulated
as usual, but these actions will not affect the transmitted or received
data. The SPE bit is readable and writable at any time, but clearing
the SPE bit while a transmission is in progress will 1) abort the
transmission, 2) reset the serial bit counter, and 3) convert port B to a
general-purpose I/O port. Reset clears the SPE bit.
1 = Serial peripheral enabled (port B I/O disabled)
0 = Serial peripheral disabled (port B I/O enabled)
LSBF — Least Significant Bit First
The LSBF bit controls the format of the transmitted and received data
to be transferred LSB or MSB first. Reset clears this bit.
1 = LSB transferred first
0 = MSB transferred first
MSTR — Master Mode Select
The MSTR bit configures the serial I/O port for master mode. A
transfer is initiated by writing to the SDR. Also, the SCK pin becomes
an output providing a synchronous data clock dependent upon the
divider of the oscillator frequency selected by the SPR0:SPR1 bits.
When the device is in master mode, the SDO and SDI pins do not
change function. These pins behave exactly the same in both the
master and slave modes. The MSTR bit is readable and writable at
any time regardless of the state of the SPE bit. Clearing the MSTR bit
will abort any transfers that may have been in progress. Reset clears
the MSTR bit, placing the SIOP subsystem in slave mode.
1 = SIOP set up as master, SCK is an output
0 = SIOP set up as slave, SCK is an input
General Release Specification
142
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Simple Serial Interface
Freescale Semiconductor