MC68HC05JJ6 Datasheet, PDF (57/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
4.8.3 Timer Overflow Interrupt
A timer overflow interrupt occurs if the timer overflow flag (TOF)
becomes set while the timer overflow interrupt enable bit (TOIE) is also
set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR.
The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set
and then followed by an access to the LSB of the timer registers (TMRL)
or by reset. The TOIE enable bit is unaffected by reset.
4.9 Serial Interrupts
The simple serial interface can generate the two interrupts:
• Receive sequence complete
• Transmit sequence complete
Setting the I bit in the condition code register disables serial interrupts.
The controls for these interrupts are in the serial control register (SCR)
located at $000A and in the status bits in the serial status register (SSR)
located at $000B.
A transfer complete interrupt occurs if the serial interrupt flag (SPIF)
becomes set while the serial interrupt enable bit (SPIE) is also set. The
SPIF flag bit is in the serial status register (SSR) located at $000B, and
the SPIE enable bit is located in the serial control register (SCR) located
at $000A. The SPIF flag bit is cleared by a read of the SSR with the SPIF
flag bit set, and then followed by a read or write to the serial data register
(SDR) located at $000C. The SPIF flag bit can also be reset by writing a
one to the SPIR bit in the SCR.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Interrupts
General Release Specification
57