MC68HC05JJ6 Datasheet, PDF (79/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Parallel Input/Output
7.3.1 Port A Data Register
The port A data register contains a bit for each of the port A pins. When
a port A pin is programmed to be an output, the state of its data register
bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin. The upper two bits of the port A data register will
always read as logical zeros.
$0000
Read:
Write:
Reset:
Alternate:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
PA5
PA4
PA3
PA2
PA1
PA0
Unaffected by Reset
KYBD3 KYBD2 KYBD1
= Unimplemented
Figure 7-1. Port A Data Register (PORTA)
KYBD0
PA5–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in the port A data
direction register (DDRA). Reset has no effect on port A data.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Parallel Input/Output
General Release Specification
79