MC68HC05JJ6 Datasheet, PDF (31/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

General Release Specification — MC68HC05JJ6/MC68HC05JP6
Section 2. Memory
2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.5 Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.6 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.7 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.8 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.9 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.2 Introduction
This section describes the organization of the memory on the
MC68HC05JJ6/MC68HC05JP6.
2.3 Memory Map
The CPU can address eight Kbytes of memory space as shown in
Figure 2-1. The ROM portion of memory holds the program instructions,
fixed data, user-defined vectors, and interrupt service routines. The
RAM portion of memory holds variable data. I/O registers are memory
mapped so that the CPU can access their locations in the same way that
it accesses all other memory locations.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Memory
General Release Specification
31