MC68HC05JJ6 Datasheet, PDF (62/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Resets
5.5 Internal Resets
The four internally generated resets are:
• Initial power-on reset function
• COP watchdog timer reset
• Low-voltage reset
• Illegal address detector
Only the COP watchdog timer reset, low-voltage reset, and illegal
address detector will also assert the pulldown device on the RESET pin
for the duration of the reset function or for three to four internal bus
cycles, whichever is longer.
5.5.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out).
Depending on a mask option, there is an oscillator stabilization delay of
16 or 4064 internal bus cycles after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of the 16 or 4064 cycle delay, the
RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. V_DD must
drop below V_POR for the internal POR circuit to detect the next rise of
V_DD.
5.5.2 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic zero to the COPC bit
of the COP register at location $1FF0. The COP register, shown in
General Release Specification
62
Resets
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor