MC68HC05JJ6 Datasheet, PDF (152/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Core Timer
10.5 COP Watchdog
Four counter stages at the end of the core timer make up the computer
operating properly (COP) watchdog which can be enabled by a mask
option. The COP watchdog is a software error detection system that
automatically times out and resets the MCU if the COP watchdog is not
cleared periodically by a program sequence. Writing a logic zero to
COPC bit in the COP register clears the COP watchdog and prevents a
COP reset.
$1FF0
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Unaffected by Reset
= Unimplemented
Figure 10-4. COP and Security Register (COPR)
Bit 0
COPC
COPC — COP Clear
This write-only bit resets the COP watchdog. The COP watchdog is
active in the run, wait, and halt modes of operation if the COP is
enabled by a mask option. The STOP instruction disables the COP
watchdog by clearing the counter and turning off its clock source.
In applications that depend on the COP watchdog, the STOP
instruction can be disabled by the stop mask option. In applications
that have wait cycles longer than the COP timeout period, the COP
watchdog can be disabled by the stop mask option. Table 10-2
summarizes recommended conditions for enabling and disabling the
COP watchdog.
NOTE: If the voltage on the IRQ pin exceeds 1.5 × V_DD, the COP watchdog
turns off and remains off until the IRQ pin voltage falls below 1.5 × V_DD.
General Release Specification
152
Core Timer
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor