MC68HC05JJ6 Datasheet, PDF (43/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Central Processor Unit (CPU)
Half-Carry Flag (H)
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The
half-carry flag is required for binary coded decimal (BCD) arithmetic
operations. Reset has no effect on the half-carry flag.
Interrupt Mask (I)
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is a logic zero, the CPU saves the
CPU registers on the stack, sets the interrupt mask, and then fetches
the interrupt vector. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. The CPU processes the
latched interrupt as soon as the interrupt mask is cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a CLI
instruction.
Negative Flag (N)
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result. Reset has
no effect on the negative flag.
Zero Flag (Z)
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
Carry/Borrow Flag (C)
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag. Reset
has no effect on the carry/borrow flag.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Central Processor Unit (CPU)
General Release Specification
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