MC68HC05JJ6 Datasheet, PDF (151/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Core Timer
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
TOF = 1/(f_OSC ÷ 2¹¹)
(microseconds)
RTI
Rate
@ f_OSC (MHz)
RT1 RT0 = f_OSC
divided
by:
4.2 2.0 1.0
MHz MHz MHz
Real-Time
Interrupt Period
(RTI)
(milliseconds)
@ f_OSC (MHz)
4.2 2.0 1.0
MHz MHz MHz
00
01
488 1024 2048
10
11
2¹⁵ 7.80 16.4 32.8
2¹⁶ 15.6 32.8 65.5
2¹⁷ 31.2 65.5 131
2¹⁸ 62.4 131 262
COP Timeout Period
COP = 7 to 8 RTI Periods
(milliseconds)
@ f_OSC (MHz)
4.2 MHz
2.0 MHz
1.0 MHz
Min Max Min Max Min Max
54.6 62.4 115 131 229 262
109 125 229 262 459 524
218 250 459 524 918 1049
437 499 918 1049 1835 2097
10.4 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the
basis of the core timer. The value of the first eight stages is readable at
any time from the read-only timer counter register as shown in
Figure 10-3.
$0009 Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR)
Power-on clears the entire counter chain and begins clocking the
counter. After the startup delay (16 or 4064 internal bus cycles
depending on a mask option), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or
four cycles of the internal bus. A timer overflow function at the eighth
counter stage allows a timer interrupt every 2048 oscillator clock cycles
or every 1024 internal bus cycles.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Core Timer
General Release Specification
151