MC68HC05JJ6 Datasheet, PDF (61/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Resets
5.3 Power-On Reset
A positive transition on the V_DD pin generates a power-on reset. The
power-on reset is strictly for conditions during powering up and cannot
be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (t_CYC) after the oscillator
becomes active allows the clock generator to stabilize. If the RESET pin
is at logic zero at the end of this multiple t_CYC time, the MCU remains in
the reset condition until the signal on the RESET pin goes to a logic one.
5.4 External Reset
A logic zero applied to the RESET pin for one and one half t_CYC
generates an external reset. This pin is connected to a Schmitt trigger
input gate to provide an upper and lower threshold voltage separated by
a minimum amount of hysteresis. The external reset occurs whenever
the RESET pin is pulled below the lower threshold and remains in reset
until the RESET pin rises above the upper threshold. This active low
input will generate the internal RST signal that resets the CPU and
peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown
device that is activated by three internal reset sources. This RESET
pulldown device will be asserted only for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
NOTE:
Do not connect the RESET pin directly to V_DD, as this may overload
some power supply designs if the internal pulldown on the RESET pin
should activate.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Resets
General Release Specification
61