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MC68HC05JJ6 Datasheet, PDF (120/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers
Analog Subsystem
NOTE:
The above two equations for the charge time, tCHG, can be combined to
form this expression for the full scale count (NFS) of the measured time
versus the full scale unknown voltage (VFS):
NFS = CEXT x VFS x fOSC / (P x ICHG)
Since a given timing method has a fixed charge current and prescaler,
then the variation in the resultant count for a given unknown voltage is
mainly dependent on the operating frequency and the capacitance value
used. The desired external capacitance for a given voltage range, fOSC,
conversion method, and resolution is defined as:
CEXT = NFS x P x ICHG / (VFS x fOSC)
The value of any capacitor connected directly to the PB0/AN0 pin should
be limited to less than 2 microfarads. Larger capacitances will create
high discharge currents which may damage the device or create signal
noise.
NOTE:
The desired type of capacitor for the ramp capacitor is any of the “poly”
film types which have both low leakage and low dielectric absorption
(somtimes referred to as memory behavior). Low-cost monolithic
ceramics are good for bypass use, but have high dielectric absorption
which makes them less desirable for an integration or storage
application. Tantalum or aluminum electrolytics have high dielectric
absorption and too much leakage, as well. For integration or storage
capacitors use capacitors which have a dielectric absorption of less than
0.01%.
The full scale voltage range for a given capacitance, fOSC, conversion
method, and resolution is defined as:
VFS = NFS x P x ICHG / (CEXT x fOSC)
Once charged to a given voltage, a finite amount of time will be required
to discharge the capacitor back to its start voltage at VSS. This discharge
time will be solely based on the value of capacitance used and the
sinking current of the internal discharge device. To allow a reasonable
time for the capacitor to return to VSS levels, the discharge time should
last about 10 milliseconds per microfarad of capacitance attached to the
PB0 pin. If the total charge/discharge cycle time is critical, then the
discharge time should be at least 1/10 of the most recent charge time.
General Release Specification
120
Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor