MC68HC05JJ6 Datasheet, PDF (65/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Resets
5.6.2 I/O Registers
A reset has these effects on I/O registers:
• Clears bits in data direction registers configuring pins as inputs:
– DDRA5–DDRA0 in DDRA for port A
– DDRB7–DDRB0 in DDRA for port B
– DDRC7–DDRC0 in DDRC for Port C *
• Clears bits in pulldown inhibit registers to enable pulldown
devices:
– PDIA5–PDIA0 in PDRA for port A
– PDIB7–PDIB0 in PDRB for port B
– PDICH and PDICL in PDRA for port C *
• Has no effect on port A, B, or C* data registers
• Sets the IRQE bit in the interrupt status and control register (ISCR)
5.6.3 Core Timer
A reset has these effects on the core timer:
• Clears the core timer counter register (CTCR)
• Clears the core timer interrupt flag and enable bits in the core timer
status and control register (CTSCR)
• Sets the real-time interrupt rate selection bits (RT0 and RT1) such
that the device will start with the longest real-time interrupt and
longest COP timeout delays
5.6.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
* Features related to port C are available only on the 28-pin MC68HC705JP6 devices.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Resets
General Release Specification
65