MC68HC05JJ6 Datasheet, PDF (71/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Operating Modes
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started up and allowed to stabilize while the LPO still clocks the MCU.
NOTE:
When switching between oscillators, the user must be careful to ensure
that the newly selected oscillator has been enabled and powered up long
enough to stabilize before shifting clock sources.
Always select the case where both OM1 and OM2 are set and remain at
this state for at least 4096 EPO clock cycles if going from the LPO to the
EPO or 16 LPO cycles if going from the EPO to the LPO.
IRQF — External Interrupt Request Flag
The IRQF flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Refer to Section 4. Interrupts for more
details.
IRQR — Interrupt Request Reset
This write-only bit clears the IRQF flag bit and prevents redundant
execution of interrupt routines. Refer to Section 4. Interrupts for
more details.
6.4 Low-Power Modes
Four modes of operation reduce power consumption:
• Stop mode
• Wait mode
• Halt mode
• Data-retention mode
Figure 6-2 shows the sequence of events in stop, wait, and halt modes.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Operating Modes
General Release Specification
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