MC68HC05JJ6 Datasheet, PDF (100/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Parallel Input/Output
7.5.2 Data Direction Register C
The contents of the port C data direction register (DDRC) determine
whether each port C pin is an input or an output. Writing a logic one to a
DDRC bit enables the output buffer for the associated port C pin. A
DDRC bit set to a logic one also disables the pulldown device for that pin.
Writing a logic zero to a DDRC bit disables the output buffer for the
associated port C pin. A reset initializes all DDRC bits to logic zeros,
configuring all port C pins as inputs.
$0006 Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 7-14. Data Direction Register C (DDRC)
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears the
DDRC7–DDRC0 bits.
1 = Corresponding port C pin configured as output and pulldown
device disabled
0 = Corresponding port C pin configured as input
7.5.3 Port C Pulldown Devices
All port C pins can have software programmable pulldown devices
enabled or disabled by the software pulldown inhibit mask option. When
enabled these pulldowns can sink approximately 100 µA. These
pulldown devices are controlled by the write-only pulldown register A
(PDRA) shown in Figure 7-3. PDICH controls the upper four pins
(PC7:PC4) and PDICL controls the lower four pins (PC3:PC0). Clearing
the PDICH or PDICL bits in the PDRA turns on the pulldown devices if
the port C pin is an input. Reading the PDRA returns undefined results
since it is a write-only register. Reset clears the PDICH and PDICL bits,
which turns on all the port C pulldown devices.
General Release Specification
100
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Parallel Input/Output
Freescale Semiconductor