MC68HC05JJ6 Datasheet, PDF (187/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Instruction Set
Table 12-6. Instruction Set Summary (Continued)
Source
Form
Operation
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
Description
(M) – $00
Effect on
CCR
H I NZC
DIR 3D ^dd 4
INH 4D
3
— — ↕ ↕ — INH 5D
3
IX1 6D ff 5
IX 7D
4
TXA
Transfer Index Register to Accumulator
A ← (X)
— — — — — INH 9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — — INH 8F
2
A Accumulator
C Carry/borrow flag
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
ff Offset byte in indexed, 8-bit offset addressing
H Half-carry flag
hh ll High and low bytes of operand address in extended addressing
I Interrupt mask
ii Immediate operand byte
IMM Immediate addressing mode
INH Inherent addressing mode
IX Indexed, no offset addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX2 Indexed, 16-bit offset addressing mode
M Memory location
N Negative flag
n Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel Relative program counter offset byte
rr Relative program counter offset byte
SP Stack pointer
X Index register
Z Zero flag
# Immediate value
∧ Logical AND
∨ Logical OR
⊕ Logical EXCLUSIVE OR
( ) Contents of
–( ) Negation (two’s complement)
← Loaded with
? If
:
Concatenated with
↕ Set or cleared
— Not affected
12.6 Opcode Map
See Table 12-7.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Instruction Set
General Release Specification
187