MC68HC05JJ6 Datasheet, PDF (160/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Programmable Timer
NOTE:
To prevent interrupts from occurring between readings of the TMRH and
TMRL, set the I bit in the condition code register (CCR) before reading
TMRH and clear the I bit after reading TMRL.
11.4 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and
alternate counter registers is shown in Figure 11-4. The alternate
counter registers behave the same as the timer registers, except that
any reads of the alternate counter will not have any effect on the TOF
flag bit and timer interrupts. The alternate counter registers include a
transparent buffer latch on the LSB of the 16-bit timer counter.
READ
ACRH
RESET
LATCH
ACRL ($001B)
READ
ACRH ($001A)
TMR LSB
($FFFC)
16-BIT COUNTER
÷4
INTERNAL
DATA
BUS
READ
ACRL
INTERNAL
CLOCK
(OSC ÷ 2)
Figure 11-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH and ACRL) shown in
Figure 11-5 are read-only locations which contain the current high and
low bytes of the 16-bit free-running counter. Writing to the alternate
counter registers has no effect. Reset of the device presets the timer
counter to $FFFC.
General Release Specification
160
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Programmable Timer
Freescale Semiconductor