MC68HC05JJ6 Datasheet, PDF (47/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Mask
Options
Reset
Power-On Logic
RESET Pin
Low-Voltage Reset
Illegal Address Reset
COP Watchdog
Software
Interrupt
(SWI)
User Code
IRQ Pin
External
Interrupt (IRQ)
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
Core Timer
Interrupts
TOF Bit
RTIF Bit
Programmable
Timer
Interrupts
ICF Bit
OCF Bit
TOF Bit
Serial
Interrupt
SPIF Bit
Analog
Interrupt
CPF1 Bit
CPF2 Bit
—
Enable
—
—
Enable
—
—
—
—
Global
Local
Hardware Software
Mask
Mask
—
—
—
—
I Bit
IRQE Bit
I Bit
TOFE Bit
RTIE Bit
ICIE Bit
I Bit
OCIE Bit
TOIE Bit
I Bit
SPIE Bit
I Bit
CPIE Bit
Priority
(1 = Highest)
Vector
Address
1
$1FFE–$1FFF
Same Priority
As Instruction
$1FFC–$1FFD
2
$1FFA–$1FFB
3
$1FF8–$1FF9
4
$1FF6–$1FF7
5
$1FF4–$1FF5
6
$1FF2–$1FF3
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
actually interrupt a lower priority interrupt service routine unless the
lower priority interrupt service routine clears the I bit.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Interrupts
General Release Specification
47