MC68HC05JJ6 Datasheet, PDF (63/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Resets
Figure 5-2, is a write-only register that returns the contents of a ROM
location when read.
$1FF0 Bit 7
Read:
Write:
Reset:
6
5
4
3
2
Unaffected by Reset
= Unimplemented
Figure 5-2. COP Register (COPR)
1
Bit 0
COPC
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
The COP watchdog reset will assert the pulldown device to pull the
RESET pin low for three to four cycles of the internal bus.
The COP watchdog reset function can be enabled or disabled by the
COP watchdog timer mask option.
5.5.3 Low-Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the
voltage on the V_DD pin falls below the LVR trip voltage. The LVR will
assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
The LVR reset function can be enabled or disabled by the low-voltage
reset mask option.
NOTE:
The LVR is guaranteed for applications where the V_DD supply voltage
normally operates above 4.5 volts. Devices that have the LVR mask
option selected cannot be operated at the 3-V operating range.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Resets
General Release Specification
63