MC68HC05JJ6 Datasheet, PDF (50/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Interrupts
4.5 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.6 External Interrupts
These sources can generate external interrupts:
• IRQ pin
• PA3–PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables these external
interrupts.
4.6.1 IRQ Pin
An interrupt signal on the IRQ pin latches an external interrupt request.
To help clean up slow edges, the input from the IRQ pin is processed by
a Schmitt trigger gate. When the CPU completes its current instruction,
it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit
in the condition code register (CCR) and the IRQE bit in the IRQ status
and control register (ISCR). If the I bit is clear and the IRQE bit is set,
then the CPU begins the interrupt sequence. The CPU clears the IRQ
latch while it fetches the interrupt vector, so that another external
interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-3 shows the logic for
external interrupts.
NOTE:
If the IRQ pin is not in use, it should be connected to the V_DD pin.
The IRQ pin can be negative edge-triggered only or negative edge- and
low level-triggered. This external interrupt sensitivity is selected with the
external interrupt sensitivity mask option.
General Release Specification
50
Interrupts
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor