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MC68HC05JJ6 Datasheet, PDF (202/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers
Electrical Specifications
13.14 SIOP Timing (VDD = 5.0 Vdc)
Characteristic
Symbol
Min
Frequency of Operation
Master
Slave
fSIOP(M)
fSIOP(S)
0.25 x fOP
DC
Cycle Time
Master
Slave
tSCK(M)
tSCK(M)
4.0 x tCYC
—
Clock (SCK) Low Time (fOP = 4.2 MHz)
tSCKL
466
SDO Data Valid Time
tV
—
SDO Hold Time
tHO
0
SDI Setup Time
tS
100
SDI Hold Time
tH
100
NOTE:
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
Typ
0.25 x fOP
—
4.0 x tCYC
—
—
—
—
—
—
Max
0.25 x fOP
1050
4.0 x tCYC
3.8
—
200
—
—
—
Unit
kHz
µs
ns
ns
ns
ns
ns
SCK
SDO
SDI
tSCK
tSCKL
tV
tHO
MSB
MSB
BIT 1
tS
VALID DATA
tH
LSB
LSB
Figure 13-5. SIOP Timing Diagram
General Release Specification
202
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Electrical Specifications
Freescale Semiconductor