MC68HC05JJ6 Datasheet, PDF (85/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Parallel Input/Output
7.4.2 Data Direction Register B
The contents of the port B data direction register (DDRB) determine
whether each port B pin is an input or an output. Writing a logic one to a
DDRB bit enables the output buffer for the associated port B pin. A
DDRB bit set to a logic one also disables the pulldown device for that pin.
Writing a logic zero to a DDRB bit disables the output buffer for the
associated port B pin. A reset initializes all DDRB bits to logic zeros,
configuring all port B pins as inputs.
$0005
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
0
0
0
Figure 7-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears the
bits DDRB7–DDRB0.
1 = Corresponding port B pin configured as output and pulldown
device disabled
0 = Corresponding port B pin configured as input
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Parallel Input/Output
General Release Specification
85