MC68HC05JJ6 Datasheet, PDF (115/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Analog Subsystem
8.5 Analog Status Register
The analog status register (ASR) contains status and control of the
comparator flag bits. These bits in the ASR are shown in Figure 8-6. All
the bits in this register are cleared by a reset of the device.
$001E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
CPF2
CPF1
0
0
CPFR2 CPFR1
COE1
VOFF
CMP2
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 8-6. Analog Status Register (ASR)
Bit 0
CMP1
R
0
CPF2
This read-only flag bit is edge sensitive to the rising output of
comparator 2. It is set when the voltage on the PB0/AN0 pin rises
above the voltage on the sample capacitor which creates a positive
edge on the output of comparator 2, regardless of the state of the INV
bit in the AMUX register. This bit is reset by writing a logical one to the
CPFR2 reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = A positive transition on the output of comparator 2 has occurred
since the last time the CPF2 flag has been cleared.
0 = A positive transition on the output of comparator 2 has not
occurred since the last time the CPF2 flag has been cleared.
CPF1
This read-only flag bit is edge sensitive to the rising output of
comparator 1. It is set when the voltage on the PB2/AN2 pin rises
above the voltage on the PN3/AN3/TCAP pin which creates a positive
edge on the output of comparator 1, regardless of the state of the INV
bit in the AMUX register. This bit is reset by writing a logical one to the
CPFR1 reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = A positive transition on the output of comparator 1 has occurred
since the last time the CPF1 flag has been cleared.
0 = A positive transition on the output of comparator 1 has not
occurred since the last time the CPF1 flag has been cleared.
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor
Analog Subsystem
General Release Specification
115