MC68HC05JJ6 Datasheet, PDF (36/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Memory
2.5 Interrupt Vector Mapping
The interrupt vectors are contained in the upper memory addresses
above $1FF0 as shown in Figure 2-5.
Address
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
Register Name
COP Register
Unused
Analog Interrupt Vector (MSB)
Analog Interrupt Vector (LSB)
Serial Interrupt Vector (MSB)
Serial Interrupt Vector ((LSB)
Timer Interrupt Vector (MSB)
Timer Interrupt Vector (LSB)
CTimer Interrupt Vector (MSB)
CTimer Interrupt Vector (LSB)
External IRQ Vector (MSB)
External IRQ Vector (LSB)
SWI Vector (MSB)
SWI Vector (LSB)
Reset Vector (MSB)
Reset Vector (LSB)
Figure 2-5. Vector Mapping
2.6 RAM
The 224 addresses from $0020 to $00FF serve as both the user RAM
and the stack RAM. The CPU uses five RAM bytes to save all CPU
register contents before processing an interrupt. During a subroutine
call, the CPU uses two bytes to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
General Release Specification
36
Memory
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor