MC68HC05JJ6 Datasheet, PDF (150/216 Pages) Freescale Semiconductor, Inc – General Release Specification Microcontrollers

Core Timer
RTIE — Real-Time Interrupt Enable
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
CTOFR — Core Timer Overflow Flag Reset
Writing a logic one to this write-only bit clears the CTOF bit. CTOFR
always reads as a logic zero. Reset does not affect CTOFR.
1 = Clear CTOF flag bit
0 = No effect on CTOF flag bit
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic one to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic zero. Reset does not affect RTIFR.
1 = Clear RTIF flag bit
0 = No effect on RTIF flag bit
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real-time interrupt rates, as
shown in Table 10-1. Because the selected RTI output drives the
COP watchdog, changing the real-time interrupt rate also changes
the counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and longest real-time
interrupt period.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent or uncertain
may cause a real-time interrupt request to be missed or an additional
real-time interrupt request to be generated. Clear the COP timer just
before changing RT1 and RT0.
General Release Specification
150
Core Timer
MC68HC05JJ6/MC68HC05JP6 — Rev. 3.2
Freescale Semiconductor