EP7212 Datasheet, PDF (95/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU)
The Left Channel Transmit FIFO Underrun Status Bit (LCTU) is set when the Left Channel Transmit
logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun
occurs, the Left Channel Transmit logic continuously transmits the last valid left channel value which
was transmitted before the underrun occurred. Once data is placed in the FIFO and it is transferred
down to the bottom, the Left Channel Transmit logic uses the new value within the FIFO for transmis-
sion. When the LCTU bit is set, an interrupt request is made.
5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO)
The Left Channel Receive FIFO Overrun Status Bit (LCRO) is set when the Left Channel Receive log-
ic places data into the Left Channel Receive FIFO after it has been completely filled. Each time a new
piece of data is received, the set signal to the LCRO status bit is asserted, and the newly received
sample is discarded. This process is repeated for each new piece of data received until at least one
empty FIFO entry exists. When the LCRO bit is set, an interrupt request is made.
5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF)
The Right Channel Transmit FIFO Not Full Flag (RCNF) is a read-only bit which is set whenever the
Right Channel Transmit FIFO contains one or more entries which do not contain valid data and is
cleared when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the
Right Channel Transmit FIFO. This bit does not request an interrupt.
5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE)
The Right Channel Receive FIFO Not Empty Flag (RCNELCNF) is a read-only bit which is set when
ever the Right Channel Receive FIFO contains one or more entries of valid data and is cleared when
it no longer contains any valid data. This bit can be polled when using programmed I/O to remove
remaining data from the receive FIFO. This bit does not request an interrupt.
5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF)
The Left Channel Transmit FIFO Not Full Flag (LCNF) is a read-only bit which is set when ever the
Left Channel Transmit FIFO contains one or more entries which do not contain valid data. It is cleared
when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the Left
Channel Transmit FIFO. This bit does not request an interrupt.
5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE)
The Left Channel Receive FIFO Not Empty Flag (LCNE) is a read-only bit which is set when ever the
Left Channel Receive FIFO contains one or more entries of valid data and is cleared when it no longer
contains any valid data. This bit can be polled when using programmed I/O to remove remaining data
from the receive FIFO. This bit does not request an interrupt.
5.16.3.13 FIFO Operation Completed Flag (FIFO)
The FIFO Operation Completed (FIFO) Flag is set after the FIFO operation requested by writing to
DAIDR2 as completed.
FIFO is automatically cleared when DAIDR2 is read or written. This bit does not request an interrupt.
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